Folded-Cascode OTA Design Tutorial for ECE GY 6403

Introduction to Folded-Cascode OTA Design

Welcome to this hands-on tutorial for designing a folded-cascode operational transconductance amplifier (OTA) as part of the ECE GY 6403 Fundamentals of Analog Integrated Circuit Design final project. In this guide, we'll walk through the entire design flow—from hand calculations to simulation validation—for a single-ended OTA that meets the target specifications: gain >70 dB, w3dB >20 kHz, slew rate >30 V/μs, phase margin >60°, and power consumption <100 μW, using a 1.2 V supply and 2 pF load. Whether you're a student tackling this assignment or a hobbyist exploring analog IC design, this tutorial provides a structured approach.

The folded-cascode topology is chosen because it achieves high gain in a single stage without sacrificing output swing. Think of it like a well-coordinated relay team: each transistor plays a specific role to amplify the input signal while maintaining stability. With the rise of low-power IoT devices and AI edge processors, mastering such designs is crucial for modern electronics.

Understanding the Folded-Cascode Topology

Before diving into calculations, let's review the core structure. A folded-cascode OTA uses a differential pair (M1, M2) that feeds into cascode transistors (M3, M4) on the output side, with a current mirror load (M5, M6) and a tail current source (M7). The "folding" refers to the way the signal path is folded to allow for a single-ended output. This configuration boosts output resistance, thereby increasing gain. For a detailed schematic, refer to Razavi's Fig. 9.18.

In today's context, analog circuits are everywhere—from smartphone audio codecs to sensor interfaces in smartwatches. The folded-cascode OTA is a building block for many such systems, making its design a valuable skill.

Hand Calculations for Transistor Sizing

We'll start with hand calculations to estimate initial transistor dimensions. Use the given process parameters (typically from a 0.18 μm CMOS process). Assume μnCox = 200 μA/V², μpCox = 100 μA/V², Vthn = 0.4 V, Vthp = -0.4 V, and λ = 0.1 V⁻¹ for both NMOS and PMOS.

Step 1: Determine Bias Current

Power consumption limit: P < 100 μW at VDD = 1.2 V, so total current I_total < 100 μW / 1.2 V ≈ 83.3 μA. Allocate about 60% to the differential pair and 40% to the cascode branch. Let's set tail current I_tail = 50 μA, so each differential transistor carries 25 μA. For the cascode branch, current I_casc = 30 μA.

Step 2: Sizing the Differential Pair (M1, M2)

For high gain, we need high transconductance gm. Use the square-law: gm = sqrt(2*μnCox*(W/L)*I_D). Target gm1 ≈ 200 μS to achieve gain. Rearranging: (W/L)1 = gm1² / (2*μnCox*I_D) = (200e-6)² / (2*200e-6*25e-6) = 4e-8 / (1e-8) = 4. So W/L = 4. Choose L = 0.5 μm (minimum for good matching), then W = 2 μm.

Step 3: Sizing the Cascode Transistors (M3, M4)

These are PMOS devices. They should have low overdrive to allow headroom. Set V_sg3 ≈ 0.3 V. Using |Vthp| = 0.4 V, overdrive V_ov = V_sg - |Vthp| = -0.1 V? That's negative, so adjust: actually for PMOS, V_sg = |Vgs|. Let's set V_sg = 0.5 V, so V_ov = 0.1 V. Then (W/L)3 = 2*I_casc / (μpCox*V_ov²) = 2*30e-6 / (100e-6*0.01) = 60e-6 / 1e-6 = 60. Choose L = 0.5 μm, W = 30 μm.

Step 4: Sizing the Current Mirror Load (M5, M6)

These are NMOS with same current as cascode branch, 30 μA. Set V_gs5 = 0.5 V (V_ov = 0.1 V). (W/L)5 = 2*30e-6 / (200e-6*0.01) = 60e-6 / 2e-6 = 30. So W = 15 μm, L = 0.5 μm.

Step 5: Tail Current Source (M7)

Carries 50 μA. Use same overdrive: V_ov = 0.1 V. (W/L)7 = 2*50e-6 / (200e-6*0.01) = 100e-6 / 2e-6 = 50. W = 25 μm, L = 0.5 μm.

These initial sizes are starting points. We'll refine them through simulation.

Simulation Setup and Iterative Sizing

Use a SPICE simulator (e.g., Cadence Spectre). Set up the schematic with ideal bias voltages (e.g., Vb1, Vb2) to test the OTA first. Perform DC, AC, and transient analyses.

AC Simulation: Gain and Bandwidth

Run an AC simulation from 1 Hz to 100 MHz. Plot the open-loop gain. If gain <70 dB, increase gm of the differential pair by increasing (W/L)1,2. If w3dB <20 kHz, increase bias current or reduce load capacitance (but CL is fixed). Trade-offs: higher gain reduces bandwidth. Iterate until both specs are met. For example, double the width of M1,2 to 4 μm while keeping L=0.5 μm, then recheck.

Phase Margin Check

Ensure phase margin >60° at unity-gain frequency. If not, add a compensation capacitor or adjust cascode bias. Often, reducing the gain of the second stage helps, but here we have a single stage. Phase margin is mainly set by the output pole. With CL=2 pF and output resistance Rout, the pole is at 1/(2π*Rout*CL). To improve phase margin, reduce Rout slightly by increasing current, but that increases power. Fine-tune the cascode bias to adjust Rout.

Slew Rate Testing

Apply a large-signal step (e.g., 0.5 V step) at the input and measure the output slope. Slew rate = dVout/dt. If <30 V/μs, increase the tail current (I_tail) or the cascode current. However, this increases power. Alternatively, reduce the load capacitance (not allowed). Typically, slew rate is limited by the tail current: SR = I_tail / CL. With I_tail=50 μA, SR = 50e-6 / 2e-12 = 25 V/μs, which is below 30. So increase I_tail to 60 μA, giving SR=30 V/μs. Adjust all transistor sizes accordingly (recalculate (W/L) for M1,2, M7).

Power Consumption Verification

Use DC analysis to measure total current from VDD. Ensure <83.3 μA. If too high, reduce bias currents (but check other specs).

Noise Analysis

Calculate input-referred noise voltage. In a folded-cascode, dominant noise sources are the differential pair and the cascode transistors. Use the formula: v_n,in² = (8kTγ)/gm1 + (2Kf)/(Cox*W1*L1*f). For thermal noise, assume γ=2/3. With gm1=200 μS, v_n,in ≈ 5 nV/√Hz. Integrate over bandwidth to get total noise. Ensure it's within acceptable limits for your application.

Transient Simulation for Low-Frequency Gain

Apply a small sinusoidal input (e.g., 1 mV at 1 kHz) and measure output amplitude. Gain = Vout_peak / Vin_peak. Should be >70 dB (i.e., >3162). If not, go back to sizing.

Designing the Biasing Circuit

Once the OTA core meets specs, replace ideal bias voltages with a current mirror. For example, use a simple NMOS current mirror to generate Vb1 (for tail) and Vb2 (for cascode). Ensure the mirror has sufficient output resistance. Use a reference current of 10 μA and scale accordingly.

Final Transistor Sizes Table

After iterations, you might have sizes like:

M1, M2: W=4 μm, L=0.5 μm
M3, M4: W=30 μm, L=0.5 μm
M5, M6: W=15 μm, L=0.5 μm
M7: W=30 μm, L=0.5 μm
Bias transistors: appropriate scaling

Layout Considerations (Bonus)

For the layout, ensure symmetry in the differential pair, use guard rings, and add dummy devices. Run DRC and LVS to verify.

Conclusion

Designing a folded-cascode OTA involves careful trade-offs between gain, bandwidth, slew rate, and power. By following this iterative process, you can meet all specifications. This skill is essential for modern analog IC design, powering everything from 5G transceivers to AI accelerators. Good luck with your project!