Digital Communications (UESTC 4004) Lab 1: Modulation/Demodulation This lab introduces you to the phase shift keying modulation technique. You shall transmit a signal using binary phase shift keying (BPSK) and then demodulate the received signal using BPSK demodulation. Bit Error Rate (BER) of BPSK will be calculated and plotted. Finally, the process is repeated for quadrature phase-shift keying (QPSK). 1 BINARY PHASE SHIFT KEYING (BPSK) 1.1 Source This component generates 10000 information-bearing uncoded bits, which are randomly drawn from the binary set {0, 1} with the equal probability. Use the MATLAB code below to generate the bits. num_bits = 10000; % Number of bits in a frame bits = rand(1, num_bits) > 0.5; % Generated information bits 1.2 Modulator This component maps binary bits to BPSK symbols. The uncoded bits are fed into a BPSK modulator to yield BPSK symbols. Use the MATLAB code below to generate the BPSK modulated bits. bpsk_sig = -2*(bits-0.5); % Modulated data 1.3 Thermal Noise. This component adds complex Gaussian noise onto the communication signal. The noise is random and should have zero mean, unity power and should vary symbol-by-symbol. Assume Signal-to-Noise Ratio (SNR) of 0 dB. Use the MATLAB code below to obtain the received BPSK signal with noise added. SNR_dB = 0; % let SNR be 0 dB N0 = 1/10^(SNR_dB/10); % Noise power with signal power of 1. a = length(bpsk_sig); Noise = sqrt(N0/2)*(randn(1,a)+1i*randn(1,a)); % AWGN Noise Rx_bpsk_sig = bpsk_sig + Noise; % Received signal Please not the multiplying factor sqrt(N0/2) in the Noise equation is used to generate normalised noise values with amplitude sqrt(N0). Sqrt is used to convert power to amplitude. Remember the relationship between power and amplitude. Task 1.1: Plot the first 10 bits of the received binary data using the MATLAB code below. [1] stem(Rx_bpsk_sig(1:10)); 1.4 Demodulation. This component first reproduces original symbols from distorted signals through employment of the minimum-distance detection algorithm. Use the MATLAB code below to demodulate the signal. Demod_bpsk_bits = Rx_bpsk_sig < 0; % Demodulated BPSK signal 1.5 Bit Error Rate (BER) This component calculates the BER by comparing the demodulated signal with the original bits produced by Source. The definition of BER is, Use the MATLAB code below to calculate the BER. Error_bits_bpsk = bits - Demod_bpsk_bits; % Find errors bits BER_bpsk = sum(abs(Error_bits_bpsk))/num_bits; % BER Task 1.2. Write down the number of error bits. Does it remain the same when you run the code multiple times? If not, why? [1] 1.6 BER vs SNR Write a MATLAB code to calculate the BER for SNR values [0: 2: 10] dB. Hint 1: You should use the components from Section 1.1-1.5 to loop through the SNR values [0: 2: 10] dB and calculate BER for each SNR value. Hint 2: Note that you have obtained the BER of BPSK for signal-to-noise (SNR) of 0 dB by following the steps in Section 1.1-1.5. Hint 3: You should use the “for loop”. Task 1.3. Plot the BER as a function of SNR for SNR = [0 : 2 : 10] dB using the MATLAB code below. Add axes labels and title to the figure. [1] semilogy(SNR,BER_bpsk,'-'); Task 1.4. Search through MATLAB Help to find another way of BPSK modulation and demodulation. Write the code for BPSK modulation and demodulation using these built-in functions. [1] 2 QUADRATURE PHASE SHIFT KEYING (QPSK) 2.1 Source Generate 10000 information bits as in Section 1.1. 2.2 Modulator This component maps binary bits to QPSK symbols. The generated bits are fed into a QPSK modulator to yield QPSK symbols. Use the MATLAB code below to modulate the bits. % Split the bits into two streams Bits1 = bits(1:2:end); Bits2 = bits(2:2:end); % QPSK pi/4 radians constellation qpsk_sig = ((Bits1==0).*(Bits2==0)*(exp(1i*pi/4))+(Bits1==0).*(Bits2==1)... *(exp(3*1i*pi/4))+(Bits1==1).*(Bits2==1)*(exp(5*1i*pi/4))... +(Bits1==1).*(Bits2==0)*(exp(7*1i*pi/4))); Task 2.1. Plot the modulated data constellation using the MATLAB code below. [1] plot(real(qpsk_sig),imag(qpsk_sig),'o'); 2.3 Thermal Noise. This component adds complex Gaussian noise onto the communication signal. The noise is random and should have zero mean, unity power and should vary symbol-by-symbol. Assume SNR of 0 dB. Use the MATLAB code below to obtain the received QPSK signal with noise added. SNR_dB = 0; % let SNR be 0 dB N0 = 1/10^(SNR_dB/10); % Noise variance with signal power of 1. a = length(qpsk_sig); Noise = sqrt(N0/2)*(randn(1,a)+i*randn(1,a)); % AWGN Noise Rx_qpsk_sig = qpsk_sig + Noise; % Received signal Task 2.2. Plot the received data constellation using the MATLAB code below and repeat for SNR values of 10dB and 20dB. [1] plot(real(Rx_qpsk_sig(1:100)),imag(Rx_qpsk_sig(1:100)),'*'); What difference do you observe with the change in SNR? Explain the reason for the difference. [1] 2.4 Demodulation. This component first reproduces original symbols from distorted signals through employment of the minimum-distance detection algorithm. Use the MATLAB code below to demodulate the signal. Bits4 = (real(Rx_qpsk_sig)
Digital Communications (UESTC 4004) Lab 3: Channel Coding The objective of this lab is to encode a message (e.g. first letter of your first name) with a given linear block code for forward error correction. The coded message is decoded using appropriate decoding scheme to recover the original message. The effectiveness of channel coding is to be demonstrated by recovering the original message accurately even in the presence of error producing noise. Introduction Linear code is an important type of block code used in error correction and detection schemes. Linear codes are applied in methods of transmitting symbols (e.g., bits) on communications channel so that, if errors occur in the communication, some errors can be detected by the recipient of the message block. A linear code of length n transmits blocks containing n bits or symbols. For example, the (7, 4) linear code is a binary linear code which represents 4 original message bits with 7 coded bits. In linear block codes, the input is a k bit block (k message bits) and output is n bit block (n coded bits) with r=n-k check bits. With a k bit message block: No of code words = 2k Block length = n Code rate = k/n The check bits are determined by some predetermined rule. U = m G where: U = code vector m = message vector G = Generator matrix which is defined as [ P | Ik ]; Ik is identity matrix of order k and P is the predefined encoding rule. Matlab Syntax: The encode function is used for encoding. The syntax is as follows. code = encode(msg,n,k,'linear/fmt',genmat) where, the codeword length is n and the message length is k. msg represents data or message. It can be in decimal or binary format. The default value for this parameter is binary. We will use binary format in this lab session. For example: Format of msg can be a binary column vector as given below. msg = [0 1 1 0 0 1 0 1 1 0 0 1]'. The ' symbol indicates matrix transpose. Format of msg can also be binary matrix with k columns. In this case format of code will be binary matrix with n columns. msg = [0 1 1 0; 0 1 0 1; 1 0 0 1]. Here k = 4. For Linear Block codes, encode function encodes msg using genmat as the generator matrix. genmat, a k-by-n matrix, is required as input. Example: The example below illustrates two different information formats (binary vector and binary matrix) for linear block code. The two messages have identical content in different formats. As a result, the two codes created by encode function have identical content in correspondingly different formats. Here k = 11. And let r = 4 r = 4; % r is the number of check bits. k = 11; % Message length n = k + r % Codeword length = 15 using formula n-k=r % Create 100 messages, k bits each. msg1 = randi([0,1], 100*k,1); % As a column vector msg2 = vec2mat(msg1,k); % As a k-column matrix % Create 100 codewords, n bits each. P =[1 1 1 1; 0 1 1 1; 1 1 1 0; 1 1 0 1; 0 0 1 1; 0 1 0 1; 0 1 1 0; 1 0 0 1; 1 0 1 0; 1 0 1 1; 1 1 0 0] genmat=[P eye(11)]; % concatenate P submatrix or predefined rule with Identity matrix. code1 = encode(msg1,n,k,'linear/binary',genmat); code2 = encode(msg2,n,k,'linear/binary',genmat); if ( vec2mat(code1,n)==code2 ) disp('All two formats produced the same content.') end Instead of randomly generating data words, you can create a data matrix of your own containing the data words that you want to encode. Exercise 1 [6+6+2+2+2+2]: Given (6,3) linear block code generated by the predefined matrix P=[0 1 1; 1 0 1; 1 1 0]. a) Encode the messages [1 1 1] and [1 0 1] through MATLAB. b) Encode all the possible messages in MATLAB and write the encoded words. MESSAGE CODE VECTOR Weight 000 001 010 011 100 101 110 111 c) The minimum hamming distance = . (see lecture for reference) d) The no. of errors this code can detect is (see lecture for reference) e) The no. of errors this code can correct is (see lecture for reference) f) The code rate = . (see lecture for reference) Exercise 2 [30]: Given below is the MATLAB code to create 8x8 matrix representing letter ‘S’. image = [ 1, 1, 1, 0, 0, 1, 1, 1; 1, 1, 0, 1, 1, 0, 1, 1; 1, 1, 0, 1, 1, 1, 1, 1; 1, 1, 1, 0, 1, 1, 1, 1; 1, 1, 1, 1, 0, 1, 1, 1; 1, 1, 1, 1, 1, 0, 1, 1; 1, 1, 0, 1, 1, 0, 1, 1; 1, 1, 1, 0, 0, 1, 1, 1]; imshow(image); Then using P = [1 1 1 1; 0 1 1 1; 1 1 1 0; 1 1 0 1; 0 0 1 1; 0 1 0 1; 0 1 1 0; 1 0 0 1] and encode function, encode your generated 8x8 matrix. You’ll have 8 coded words of 12 bits each. Remember the size of P is k x (n-k). This information will be helpful in calculating n and k. 3) Decoding linear block codes: Let Z stands for the received vector when a particular code vector U has been transmitted. Any transmission errors will result in Z ≠ U. The decoder detects or corrects errors in Z using stored information about the code. A direct way of performing error detection would be to compare U with every vector in the code. This method requires storing all 2k code vectors at the receiver and performing up to 2k comparisons. But efficient codes generally have large values of k, which implies rather extensive and expensive decoding hardware. More practical decoding methods for codes with large k involve parity check information derived from the code’s P submatrix. Associated with any systematic linear (n,k) block code is a(n-k)×n matrix called the parity check matrix H. This matrix is defined by H = [Ir | P’] Where Ir is the r × r identity matrix and n - k = r. The parity check matrix has a crucial property for error detection which is ZHT = (0 0 0 0 …… 0) provided that Z belongs to the set of code vectors. However, when Z is not a code vector, the product ZHT contains at least one nonzero element. Therefore, given HT and a received vector Z, error detection can be based on S = Z HT an r-bit vector called the syndrome. If all elements of S equal zero, then either Z equals the transmitted vector U and there are no transmission errors, or Z equals some other code vector and the transmission errors are undetectable. Otherwise, errors are indicated by the presence of nonzero elements in S. Thus a decoder for error detection simply takes the form. of a syndrome calculator. We develop the decoding method by introducing an n-bit error vector E whose non zero elements mark the positions of transmission errors in Z. For instance, if U = (1 0 1 1 0) and Z = (1 0 0 1 1) then E = (0 0 1 0 1). In general, Z = U Å E And conversely, U = Z Å E Substituting Z = U + E into S = ZHT, we obtain S = (U Å E)HT S =UHT Å EHT S = EHT which reveals that the syndrome depends entirely on the error pattern, not the specific transmitted vector. Syndrome decoding example An (8, 4) binary linear block code U is defined by systematic matrices: 0 1 1 1 | 1 0 0 0 1 0 0 0 | 0 1 1 1 G = 1 0 1 1 | 0 1 0 0 H = 0 1 0 0 | 1 0 1 1 1 1 0 1 | 0 0 1 0 0 0 1 0 | 1 1 0 1 1 1 1 0 | 0 0 0 1 0 0 0 1 | 1 1 1 0 Consider two possible messages: m1 = [0 1 1 0] m2 = [1 0 1 1] u1 = [0 1 1 0 0 1 1 0] u2 = [0 1 0 0 1 0 1 1] Suppose error pattern e = [0 0 0 0 0 1 0 0] is added to both code words. z1 = [0 1 1 0 0 0 1 0] z2 = [0 1 0 0 1 1 1 1] Calculating the syndrome using S = ZHT. Here Z is the received erroneous code word. s1 = [1 0 1 1] s2 = [1 0 1 1] The syndromes are the same and equal column 6 of H, so decoder corrects bit 6. Exercise 3 [20+20+10]: Write MATLAB code to create a syndrome table that shows all the possible errors that the coder in above example could correct. You may seek help from the built-in MATLAB function(s). Once you know the error patterns, generate the syndrome vector corresponding to each error pattern. If z = [ 0 1 1 1 0 1 1 0] is the received vector, what is the corresponding syndrome and at which position is the error, if any? Also, write the vector after correcting the error. MATLAB Help: 1) DECODE: Function: Block decoder Syntax msg = decode(code,n,k,'linear/fmt',genmat,trt) [msg,err] = decode(...) [msg,err,ccode] = decode(...) [msg,err,ccode,cerr] = decode(...) Description: See MATLAB help 2) SYNDTABLE: Function: Produces syndrome decoding table Syntax: t = syndtable(h) Description: See MATLAB help 3) gen2par Function: Convert between parity-check and generator matrices Syntax parmat = gen2par(genmat) genmat = gen2par(parmat) Description: See MATLAB help
Digital Communications (UESTC 4004) Lab 2: Channel Equalization A. Introduction Intersymbol interference (ISI) refers to interference caused by the time response of the channel spilling over from one symbol into adjacent symbols. ISI has the effect of introducing errors between the data sequence at the receiver output and the original data sequence applied to the transmitter. Hence, unless corrective measures are taken, intersymbol interference could impose a limit on the attainable communication rate. To compensate the channel induced ISI we use the technique known as Equalization. The objective of this lab is to design and investigate the performance of a type of equalizer known as Zero Forcing Equalizer. B. Create Output Pulse The effect of a filter on a waveform. can be viewed in the time domain. The output y(t) resulting from convolving an ideal input pulse x(t) shown in Figure 1 (having amplitude Vm and pulse width T) with the impulse response of a first-order low-pass filter can be written as where and is the time constant of the channel. The amplitude of the impulse response Vm = 1, the pulse period T = 1, and the time constant of the channel T = 1. Given that the sampling time in simulation dt = 0.01, plot the output response y(t) for 0 ≤ t ≤ T + 5T by using the following MATLAB code. Note that T = tau in the MATLAB code Fig. 1. Ideal pulse. c = [Vm*(1 - exp(-[dt : dt : T]'/tau)); Vm*(1 - exp(-T/tau)) *exp(-([T + dt : dt : T+5*tau]' -T)/tau)]; figure() plot(dt:dt: T+5*tau, c); ylim([0 1]); Next, for fixed pulse period T = 1, also plot the output response for T = 0.2, 10 Comment on the resulting figures. Hint: Compare the output response with the input pulse x(t) in Fig. 1. Ensure that plots have the same limit on the y-axis. Note that T = 1 for the rest of the lab unless otherwise stated. C. Generate the Received Signal with Intersymbol Interference In the previous section, we have shown the output response y(t) of an ideal input pulse. The channel impulse response c(t) is equivalent to the received impulse y(t) of an ideal pulse, i.e., c(t) = y(t) In this section, you will create the received signal with intersymbol interference. First generate N = 1000 BPSK bits/symbols. Hint 1: Use the rand function in MATLAB. Note that v rand(1,N) > 0.5 will generate 0, 1 with equal probability, where N is the number of bits Hint 2: For BPSK modulation, the N symbols/bits can be obtained as b = 2 * v - 1 such that 0 → -1, 1 → 1 Let T = 1 be the BPSK symbol/bit period. To create the received signal with ISI, you should consider the following · The number of simulation samples over one BPSK symbol nT can be obtained as nT = dt/T, where dt is the time in the simulation. Here we set dt = 0: 01 · nc denote the length of the vector with the channel impulse response, i.e., nc = length(c) · x is an nx x 1 matrix of the received signal with ISI where nx = N * nT The received signal with ISI can be obtained using the following MATLAB code x = zeros(nx, 1); for n=1:N i1 = (n-1)*nT; y = [zeros(i1,1); b(n)*c; zeros(N*nT-i1-nc,1)]; x = x + y(1:nx); end Note that due to the effects of system filtering, the tail of a pulse can smear into adjacent symbol interval, thereby interfering with the detection process and degrading the error performance; such interference is termed intersymbol interference (ISI). Even in the absence of noise, the effect of filtering and channel-induced distortion lead to ISI. Next plot the eye diagram with no equalization. Hint: you can use the following MATLAB code figure() hold on for n=1:2:N plot(dt : dt : 2, x((n-1)*nT+1:(n+1)*nT)); end Compute the number of received bit in error by comparing the transmitted bit and the sampled received bit (with ISI) at intervals such that xT = x(nT:nT:nx); Hint: Use the following MATLAB code xT = x(nT:nT:nx); dz0 = find(xT < 0); dz1 = find(xT >= 0); db = b; db(dz0) = -1*ones(size(dz0)); db(dz1) = +1*ones(size(dz1)); err = find(db ~= b); fprintf('No equalizer: %d bits out of %d in error ', length(err), N); Now consider the case with T = 0.2, 10. Compute the number of bits in error for each case Plot the eye diagram for T = 0.2, 10 and comment on the performance. Use a flowchart to describe key steps in the MATLAB code you have implemented D. Implement Zero Forcing Equalizer In this section, you will implement the zero-forcing equalizer and show its effect by plotting the Eye diagram. You should follow the following process · Define the length of the zero-forcing equalizer Ne. Note that Ne should be sufficiently large so that equalizer spans length of the ISI. You can select Ne = 5*tau/T; · Get samples of the channel response ct to solve for the zero forcing (ZF) equalizer weight. Hint the samples cT = c(nT:nT:nc); · Using the sample of the channel c(t) and the toeplitz function in matlab, construct the matrix on the right side of the ZF equalizer equation C. Hint: C = toeplitz([cT(1:end)' zeros(1,2*Ne+1-L)],[cT(1) zeros(1,2*Ne)]); L is the length of the matrix cT , i.e., L = length(cT); · Construct the matrix on the left side of the ZF equalizer weight equation. Hint: z = [zeros(Ne,1); 1; zeros(Ne,1)]; · Solve for the ZF equalizer weight w. Note that z = Cw and w = inv(C)*z Next you should process the received signal with the ZF equalizer through the following steps. · Obtain the impulse response of the equalizer hzf which can be generated as hzf = kron(w, z0);where z0 = [1; zeros(nT-1,1)]; · Perform. the equalization using the convolution function, i.e., yall = conv(x, hzf); · Select the output y = yall((Ne*nT+1):(length(yall)-(Ne+1)*nT)+1); Next plot the eye diagram for the equalized signal and compare the result with the case without an equalizer. Hint: Use the following MATLAB code figure() hold on for n=1:2:N plot(dt : dt : 2, y((n-1)*nT+1:(n+1)*nT)); end Compute number of received equalized signal in error by comparing the transmitted bit b and the sampled equalized signal yT at intervals such that yT = y(nT : nT : nx). Hint: Use the following MATLAB code yT = y(nT:nT:nx); dz0 = find(yT < 0); dz1 = find(yT >= 0); db = b; db(dz0) = -1*ones(size(dz0)); db(dz1) = +1*ones(size(dz1)); err = find(db ~= b); fprintf('ZF equalizer: %d bits out of %d in error ', length(err), N); Use a flowchart to describe key steps in the MATLAB code you have implemented.
Data Science & Machine Learning in Finance (ACCFIN5246) Course Project – Spring 2025 1 Instruction (I) Deadline: 4 March, noon. (II) This course project counts towards (i) 35% (via quiz format) + (ii) 50% via the reflective report, to the overall course grade. This is an individual assessment. Answer all ques- tions. Both submissions (i)-(ii) to be made electronically via the course Moodle page. Each part specifies further instructions. (III) Results should be reported in a clear format. Avoid reporting numbers in the ‘scientific format’ e.g. 7 .2031e-06. All reported numbers should be rounded to two decimal points. For example, report 0.00 in place of 7 .2031e-06. (IV) The grading in (i) is carried out strictly based on the precision of results (with minor variational tolerance). The reflective component (ii) is graded according to the clarity of arguments, connectedness of the interpretations to the underlying quantitative frame- work, clarity of the visualisations, and financial implications. The final part is graded based on the relevance of finance analysis supported by the methodologies and empirical results. 2 Data: Acquisition and Description All data series are to be researched thoroughly to ensure consistency with other variables, in terms economic interpretations, units, frequency, and other characteristics. The study focus time-span is 2000-2023. The cleaned dataset should be arranged in both daily and weekly frequencies in preparation for various results requested in Section (3.2). 2.1 Dataset 1 (DS1) The first dataset (DS1) is provided in the course project, including 63 variables and summaris- ingMSFT public stock transactions and market information. The data is acquired from WRDS- CRSP universe. DS1 only includes data entries — with the data description and data dictio- nary provided separately via WRDS: Data Description Guide. All computations and analyses should explicitly take into account the instructions provided in the data description guide. The dataset provides part of the variables needed to gather descriptive and inferential statis- tics. The data covers 2000-01-03 to 2023-12-29, on a daily basis. The project set-up below refers to several variable (not all) included in the DS1,for example: • Calendar Date: Trading day (date) • Microsoft stock price (PRC) • S&P500 composite market index return (sprtrn) • Outstanding shares (Shrout) • Ask, Bid Quotes (ASK, BID) • Market index returns data on a value-weighted market portfolio including dividends reinvested (variables vwretd) and excluding dividends (variable: vwretx). This is based on the US Total Market Index produced by the CRSP that comprises nearly 4,000 con- stituents across mega, large, small and micro capitalizations, representing nearly 100% of the U.S. investable equity market. The dataset includes additional variables. The course project will not require using those vari- ables where there are no entries across an entire column. 2.2 Risk-free Rate (DS2) Interest rates, associated with US 1-, 2-, and 10-year maturity treasuries. 2.3 US CPI (DS3) The US consumer price index maybe used to transform. nominal data to real terms. 3 Data Preparation 3.1 Data Cleaning and Arrangement • Construction of the financial dataset should takes into account the possibility of sporadic observations. When multiple series of disparate frequencies are used within the same model, variable timestamps must be aligned. • The combined dataset including all variables alongside a common timeline may amount to encountering missing values and other irregularities. • The definition of (daily) log-return provides a measurement for value changes between consecutive observation points which may not necessarily be adjacent points in time (days, weeks, etc.) as a result of discarding missing values or synchronising an unbal- anced set of observations. • Assume the following when required: – a ‘calendar year’ comprises exactly 52 weeks, this may amount to minor discrepan- cies since, year ≈ 52.17 weeks – disregard this discrepancy. – a trading year comprises 250 days, thus disregard any variations such as leap years or public holidays affecting the number of trading days. – a trading month is 25 days and a trading week is 5 days, disregard variations beyond these settings. • Weekly log-returns are defined as the percentage value change between a week’s first trading day to next week’s first trading day. 3.2 Main Variables Based on the datasets and instructions in Sections (2)-(3.1), construct the following variables: • Construct the daily MSFT log-returns (rt) using the price (PRC) as the basis variable. • Denote the simple market net return using the (sprtrn) as (m,t). • Construct log-returns using (m,t). Denote the market log-return as (rm,t). You may need to use the S&P index value at 2000-01-03 which was equal to 1455.22. • Construct the net risk-free rate, using DS2 (variable: DGS2) denoted as (rf,t) • Construct daily excess MSFT log-returns rt = rt − rf • Construct daily excess market log-returns rm,t = rm,t − rf. • Construct the net inflation rate, using DS3 (variable: CPILFESL), by applying the log- return method, and denoted by πt. At this stage, the dataset is arranged to have daily observations: {rt , m,t, rm,t, rf,t,xrt,xrm,t,πt} also extended to include other variables provided is DS1 and DS2. If there are occasional miss- ing values, investigate whether these are due to coding issues (for example, πt must always be populated at all days in the dataset above) or whether there has been unreported values between the asset, market and the riskfree returns. 4 Objective Component (35%) Each question carries an equal weight and according to the University Objective Grading Scale. Provide the answers to the following questions via the Objective Component Section on the Course Moodle page. Note For all of the questions (Q1.-Q20.), any numerical answer must be rounded to the closest two decimal points. The computation is carried out based on daily frequency and for whole sample timespan. Q1 . Average stock price (as recorded by the PRC variable). Q2 . Average outstanding shares (as recorded by the SHROUT variable). Q3 . Final stock price on 2023-12-29 (as recorded by the PRC variable). Q4 . Final outstanding shares balance on 2023-12-29 (as recorded by the SHROUT variable). Q5 . Average ask-bid spread (as recorded by the ASK−BID variables). Q6 . Final ask-bid spread (as recorded by the ASK−BID variables) on 2023-12-29. Q7 . Construct the log-returns based on the PRC variable, and similarly, percentage changes in the outstanding shares (constructed following a similar method as the log-returns of the prices). Run a simple linear regression using OLS where the outcome variable is the log-returns on the prices, on an intercept and an independent variable which is the percentage change of the outstanding shares. Report the slope coefficient. Q8 . Select the units of the coefficient reported in the previous part. Q9 . The lowest stock price value in the whole sample Q10 . The highest stock price value in the whole sample, occurred in which year? Enter the year value only (4 digits, e.g. 2000 without any month or day). Q11 . Construct the log-returns based on the PRC variable on the original frequency, and similarly, include the percentage changes in the S&P market index (sprtrn, noting the value under this variable is already in percentage changes). Run a simple linear re- gression using OLS where the outcome variable is the log-returns on the prices, on an intercept and an independent variable which is the percentage changes in the S&P market index. Report the slope coefficient. Q12 . Construct the log-returns based on the PRC variable on the original frequency, and similarly, include the percentage changes in the S&P market index (sprtrn, noting the value under this variable is already in percentage changes). Run a simple linear re- gression using OLS where the outcome variable is the log-returns on the prices, on an intercept and two independent variables which are the percentage changes in the S&P market index. Report the slope coefficient, on the percentage changes in the S&P market index. Q13 . Construct the dividend-yield (DP ratio). Report the sum of DP ratios. Compute the following financial returns. Assume an investment value of $1, invested in at the start of 2000-01-03 and liquidated on 2023-12-29. For net returns, this should be computed with two decimals, for example 20.75% is 0.2075 and rounded and entered as 0.21. Q14 . Total nominal net return associated with the S&P market index. Q15 . The average (annual) nominal net return associated with the S&P market index (ac- count for compounding). Q16 . Nominal net return associated with the MSFT stock. Q17 . Real net return associated with the S&P market index. Q18 . Real net return associated with the MSFT stock. Q19 . The average (annual) real net return associated with with theMSFT stock (account for compounding). Q20 . Total real excess net return for the MSFT stock. 5 Reflective Component (50%) 1. Investigate the ASK-BID variable and comment if the behaviour of the data series over the full sample is reasonable. Do you observe any irregularities? Explain. 2. Consider the model characterised by the following specification: xrt = αw + βwxrm,t + ut (1) note that the object of interest is the time-varying feature of the coefficients α-w and β-w. In particular, β-w summarizes the conditional relationship, given a rolling window incorpo-rating a consecutive but limited span of data, between the market excess log-return and an individual investment excess log-return. The diagram below provides an illustration to describe overlapping windows (w), including a calendar year of data: Figure 1: The timeline illustrates a rolling window set-up, where each iteration includes a consecutive 52 weekly datapoints, where W1, W2, ... refer to week numbers throughout the entire sample and wi refer to a rolling window identifier. Focus on the abnormal returns^(α)w as the outcome variable, and the remaining variables included in DS1-DS3. Provide a shrinkage and regularisation methodology to explain the variations of the abnormal returns on the weekly frequency. • The proposed methodology and estimation should not introduce new data, however the existing variable maybe combined or transform. (lagged data is acceptable). • Provide a financial rationale why the variables are selected. • Provide a quantitative evaluation on how much the model set-up to predict the ab- normal returns may amount to increasing the financial performance. Benchmark this output versus the value in Q.20 established under Section (4). 6 Background Reading • Lecture slides • WRDS: Data Description Guide • S&P U.S. Indices Methodology • Microsoft Annual Report (2023) • Frank A Wolak. An exact test for multiple inequality and equality constraints in the linear regression model. Journal of the American Statistical Association, 82(399): 782–793, 1987 • Chong Kiew Liew. Inequality Constrained Least-Squares Estimation. Journal of the American Statistical Association, 71(355):746–751, 1976. ISSN 01621459. URL http: //www.jstor.org/stable/2285614
Reflective Component Assessment Brief 2024/2025 Please make sure you carefully read and understand the question or task. If you have unanswered questions, please post these on the course Moodle Discussion Forum, and we’ll respond. Assignment Information Course Code ACCFIN5246_2A Course Title Data Science and Machine Learning in Finance Weighting 50% Question release date 06-02-25 Submission date: 04-03-25 Grades and Feedback to be released on: 25-03-25 Word limit Reflective component between, suggestions is 1200-1500. Action to be taken if word limit is exceeded No penalty QUESTION/ DESCRIPTION OF ACTIVITY • The part of the project is an individual assignment. The course project includes two components, where this document provides briefing about the Reflective Component accounting for 50 % of the overall course grade. • The Course project describes developing a number of numerical and computational quantities. The course project sheet provides specific instructions about the project development. The reflective component requires development of the methodologies, financial interpretations and explanations of the results. ASSESSMENT RUBRIC/ CRITERIA Rubric 1: General Assessment Criteria. Number of questions in exam (total) 2 Number of questions to be answered 2/2 Weighting of questions 10% and 40% Other Exam Preparation Advice Reading items cited in the course project sheet FEEDBACK METHOD The project shares many similar characteristics at the practical projects attempted during the classes. Feedback on submitted work is provided via Moodle. Students are welcome to attend the lecturer’s office hours to receive further feedback.
Java Lab 2 Due: Friday, September 1, 11:00 AM EDT In this lab, you will practice with a few of the String and StringBuilder methods. 1. Create a project named Lab2. Download the file StringStuff.java from Canvas and copy it to the src directory. 2. Run the program; enter "gopher" when prompted for a string. What do the boolean values tell you? 3. Create a new String variable s3 and set it equal to the phrase "The name of my pet ". Then: - display s3 - display s3 in all upper case - display s3 again: has it changed? Why or why not? - set s2 to s3 concatenated to " " and to s1 (that is, s3 first) and display it - concatenate the string " is Fluffy Face" (notice the extra leading space) to s2. Display it. - display s2 in all lower case. - display s2 with all "e" characters replaced by "XYZ". Display s2 again – has it changed? 4. Create a new String variable s4 and set it equal to "Barrett,Sales,#44132,8/22/2018". Then: - display s4 - create an array of strings named slist (like this: String[] slist) and set it equal to the result of splitting s4 on the comma character. Then display slist with this code: for (String str: slist) { System.out.println(str); } How many lines were printed? - create a new String[] date and set it equal to slist[3] split on the "/" character. Display the parts of date with similar code to the above loop. - create a new String s5 and set it equal to the parts of slist concatenated together – the parts are accessed by slist[0], slist[1], etc. Display s5. 5. This problem tests the relative performance of String concatenation versus StringBuilder appending. Use this code to time 10,000 String concatenations: long startTime = System.currentTimeMillis(); for (int i = 0; i
Math 132A Assignment 4 Due: Thursday, February 8th at Midnight on Gradescope. Don’t forget you will not have a computer on the midterm so it ’s important you know how to do these by hand and calculator. 1. Recall from class that we discussed the general quadratic function f : Rn → Rn defined by for an n × n symmetric matrix Q and b ∈ Rn. (a) Prove that ∇f (x) = Qx − b and ∇2 f (x) = Q. (b) Starting from x(0) = (1, 1.5)T, determine the the first three iterates in the method of steepest descent applied to such an f with 2. Apply three iterations of the method of steepest descent to the function starting at x(0) = (0, −2). 3. The function is known as Rosenbrock ’s function or the banana function. This function is considered “nasty” and is often used to test algorithms. (a) Prove that (1, 1) is the unique global minimizer of f. (b) With a starting point of (0, 0)T, apply two iterations of Newton’s method. (c) Repeat part (b) with the method of steepest descent but with fixed step size α = 0.05.
CO 101 Project 1 Mass Communication, Advertising & Public Relations Module This project will use the knowledge and skills you obtained from content and assignments in the Mass Communication, Advertising & Public Relations unit to write a 625-675 word crisis communication plan. You will rely on part of the Strategic Plan Framework you learned about at the beginning of MAP (publics, objectives, message, communication pathways) to complete this project. You are part of the communication team for a major multinational company. This company is experiencing a crisis that has now received media attention due to a whistleblower coming forward. A whistleblower is usually a current or former employee of an organization who comes forward with information about their employer that could be damaging to the employer because it is illegal, immoral, illicit, unsafe and/or fraudulent. Your job is to provide a summary of a crisis communication plan to address the situation. You will be coming up with a hypothetical crisis related to this scenario. The crisis needs to be significantly damaging to the organization, impact multiple publics, and require a PR/advertising response. Do NOT use outside research for this plan. Write concisely and divide your paper into four sections that are clearly labeled A through D. Do NOT repeat the prompts in your paper. Part A: List a major multinational company (real or fictional) you are working for and the type of crisis you are experiencing. In one sentence, list the name of the company, what they do, the name of the CEO of the company, and the city, state, and country of their headquarters. In two to three sentences, list a hypothetical crisis directly related to the above scenario, briefly describe the content of the whistleblower allegations, what they said, and explain why it could be damaging to the company. Part B : Identify three key, distinct, internal and/or external publics (not individuals or a small group of people) associated with such an event (not the media), and clearly explain why it is important for the company to communicate with them in this situation through a PR or Advertising campaign (refer to Assignments 2 & 3). You do NOT need to specify whether the public is internal or external. Remember that not all publics require a PR/Advertising campaign to be reached. The publics can overlap, but they cannot be identical. The publics must represent logical choices and be specific. However, the publics should not be too specific, for no clear reason. For example, people aged 31-32 is not a logical choice as this age group is unlikely to have distinct communication needs. That said, age can be used to segment your publics, if appropriate in this case. Part C: For each public, state and explain a communication objective that requires a PR or advertising campaign to achieve it (refer to Assignments 2 & 3). Each objective statement must be one sentence long (not more) and must follow the rules discussed in class and must be logical and realistic for each public. The proposed time period must be realistic and specific. For example, if you propose “within two months,” then clarify when the two-month period starts. After stating each communication objective, clearly explain why it is a good objective in 1-2 sentences. Part D: As a member of the communication team of the company you chose, create a mock-up message (refer to Assignments 2 & 3). Include the following for this section: 1. Clearly identify ONE key public articulated in Part B for this message. 2. Clearly identify ONE medium that will be used to disseminate the message and explain the rationale behind your choice. 3. Create a textual message that achieves the objective you stated for that public in Part C (not to exceed 100 words). Don’t describe the message and do not use any images. Instead, write it. Clearly incorporate either ethos, pathos, or logos in this message (include only one). Add one line to explain which one you used and clearly specify where it is present. Deliverable: • 625-675 word crisis communication plan (approximately 2 pages), double-spaced, Times New Roman, 12 point font, with 1” margins. • Your header must include: 1) your name, 2) your TA’s name and your discussion section letters (AC, BD, etc.), • Use complete sentences and proper grammar. • Do not use personal pronouns like I/me/my/our/your, etc. (except for the mock-up message) • Be sure to save a screenshot of the upload confirmation page for your own records. Grading Balance 70% Paper 4% Part A 21% Part B 24% Part C 21% Part D 30% Grammar and logical flow on a sentence, paragraph, and document level 10% Paper organization and style. 20% Grammar errors Things we will be checking under the grammar rubric for this project (unless otherwise noted): • Incorrect verb tense • Lack of subject/verb agreement • Run-on sentences • Sentence fragments • Nonsensical phrasing that makes a sentence difficult or impossible to understand • Missing articles (a/an/the) • Typos • Incorrect capitalization • Incorrectly used semicolons and apostrophes • Punctuation placed to the right of closing quotation marks • Missing punctuation at the end of a sentence • Personal pronouns like I/me/my/our/your, etc. (except for the mock-up message)
Digital Communications (UESTC 4004) Lab 4: Project Demo and Evaluations The objective of this lab is to design a digital communication system by yourself according to some requirements. After designing, you should evaluate its performance and think about how to improve it. SCENARIO AND REQUIREMENTS Imagine that you are in the main building of the university, and you need to transmit a picture over the air to your roommate in the dormitory. The picture can be your profile picture, your selfie, or any other picture that you like. The signal will pass through a channel with additive white Gaussian noise. To receive the image with a low bit error rate (BER), you need to design an orthogonal frequency-division multiplexing (OFDM) based communication system. Design the system using appropriate modulation scheme and FFT size N to ensure the system supports at least 100 Mbps data rate. You have 10 MHz bandwidth available to you. Please consider using 12 subcarriers as pilots for channel estimation. Also, add a cyclic prefix of 0.4µsec with each OFDM symbol to suppress Inter Symbol Interference (ISI). Perform. the tasks and report the findings as advised below: 1.1 Draw the block diagram representing all the blocks of your proposed system. 1.2 Show your OFDM system design calculations. 1.3 Display the original image and the received image. 1.4 Draw the BER curve for Eb/No from 0 to 20 dB. We want to improve the bit error rate performance using an appropriate channel coding scheme. The channel coding can cost in terms of data rate drop and increased bandwidth requirement. Given that the data rate must not drop below 100 Mbps, we would need to increase the bandwidth to accommodate channel coding cost. Suppose the maximum available bandwidth is 20 MHz, perform. the tasks and report your findings as mentioned below: 1.5 Propose a suitable channel coding scheme for this scenario. 1.6 Repeat Step 1.3 and 1.4 for your proposed encoded OFDM system. 1.7 Critically evaluate your design choices and their impact on system performance. 1.8 Give the code of your project. Hint 1: You may use some key methods, including but not limited to, what you have learned from previous labs and lectures, such as modulation, and channel coding. Hint 2: You may require the skills to deal with images. Feel free to use search engines for support.
CENG0006: Coursework Process Flowsheeting with Recycle and Nonlinear Equations Exercise - 1: Nonlinear Equation - van der Waals Equation of State [20] Using GAMS (as a programming language) solve for V the following van der Waals equation of state for ammonia at 10 atm and 250°C by using Secant Method where two initial guesses for V are 2.50 and 2.51. (P + a/V2) (V- b) = RT a = (27/64) (R2 Tc2/Pc) b = RTc/(8Pc) Given: R = 0.08206 atm l K-1 mol-1, P = 10 atm, T = 523 K, Tc = 407.5 K, Pc = 111.3 atm, a = 4.238448, b = 0.037556. Provide the formulation of the problem, the solution obtained, the GAMS (.gms) code and progress of the iterations in the report. Resolve the problem from different initial guesses. Analyse and discuss the effect of initial guesses on the final solution and on the convergence to the final solution. These values of initial guesses have to be chosen by you. GAMS codes for this part are not required to be submitted. Exercise - 2: Simulation of an Equilibrium Reactor [15] Consider the following reactor where stream 2 is pure ethane. Ethane is dehydrogenated to ethylene and acetylene in the following pair of catalytic reactions: C2H6 ↔ C2H4 + H2 C2H6 ↔ C2H2 + 2H2 Let A represent ethane, B ethylene, C acetylene and D hydrogen. The reactions proceed such that the product gas composition satisfies the following equilibrium conditions: where y denotes mole fraction. Let Y1and Y2 denote extent of first and second dehydrogenation reactions respectively. Assume 100 kmol/hr of ethane is entering the reactor. (i) Provide mass balance equations for the reactor in terms of component flowrates, and Y1and Y2 . (ii) Write equations for y, the mole fractions, in terms of the component flowrates, and Y1and Y2 , and substitute the equations obtained into the equilibrium conditions given above to obtain equations in terms of Y1and Y2 . Formulate the resulting equations in GAMS and solve the equations: (a) using the CNS solver to compute values of Y1and Y2 , and (b) using Newton’s method by using GAMS as a programming language to compute values of Y1and Y2 . Provide the GAMS (.gms) codes in the report. Exercise - 3: Process Flowsheeting with Recycle [40] In this exercise you have to solve the mass balance for the following flowsheet: The reactor considered in this flowsheet is the same as the reactor in the previous Exercise except that the assumption of 100 kmol/hr of ethane entering the reactor does not hold due to the recycle (stream-5). A 100 kmol/hr feed (stream-1) of pure ethane is mixed with the recycle (stream-5) containing pure ethane, and the mixed stream (stream-2) goes to the reactor where the dehydrogenation reactions as explained in the previous Exercise take place. The outlet (stream-3) from the reactor goes to the separator which separates 95% of unreacted ethane from ethylene, acetylene, and hydrogen and recycles the separated ethane to the mixer. PART A: Write the mass balance for this problem and submit it as apart of the report. Carry out degrees of freedom analysis and if it is not zero then make it zero by specifying some variables or removing some specification, as appropriate. Submit degrees of freedom analysis in the report. PART B: Sequential Modular Process Flowsheeting - using GAMS as a programming tool Solve the problem by using GAMS by using stream 5 as the torn stream. Plot ε, the error, as a function of iteration counter k, where where F5(k)(i) denotes the flowrate of component i in stream 5 computed in iteration number k. In this case you could define the unknown variables as PARAMETERS in GAMS. To start the calculations, guess initial values for stream 5 component flowrates and then sequentially calculate the remaining stream component flowrates. Prepare a short report containing the plot mentioned above and the values of the converged flowrates of all the components in all the streams. Decide a sensible value of ε as the convergence criteria - if you cannot decide, then try different values and discuss your observations in the report. Provide the GAMS (.gms) code in the report. PART C: Equation Oriented Process Flowsheeting - using GAMS as a modelling tool Resolve this problem using the Equation Oriented approach in GAMS using the CNS solver. Provide the GAMS (.gms) code in the report. Exercise - 4: Solving Simultaneous Nonlinear Equations [25] Consider the following three simultaneous nonlinear algebraic equations in three variables: Carry out one iteration of the Secant method by hand, using the starting point: Do not invert the Jacobian matrix and instead calculate the step vector; you may calculate the step vector by hand or use GAMS to calculate the step vector - if you use GAMS then provide the GAMS (.gms) code in the report.
Assignment 1 - Case Study (Individual Assignment) Dynamic Lot Sizing The dynamic lot-size model in inventory theory, is a generalisation of the Economic Order Quantity (EOQ) model that takes into account that demand for a product varies over time. Dynamic lot sizing sometimes refers to as ‘Time-Varying Demand’ as well. In contrast to EOQ model where demand is constant, in the time-varying deterministic demand model, demands of various periods are unlike. The variations depend on different reasons. For example, production on a contract, which requires that certain quantities are delivered on specified dates. Note that we are still considering deterministic demand, i.e., all variations are known in advance. In the basic models, lead-time is disregarded. When dealing with lot sizing for time-varying demand, it is generally assumed that there are a finite number of discrete time steps, or periods. A period may be, for example, a day or a week. We know the demand in each period, and for simplicity, it is assumed that the period demand takes place at the beginning of the period. There is no initial stock. When delivering a batch, the whole batch is delivered at the same time. The holding cost and the ordering cost are constant over time. No backorders are allowed. We shall use the following notation: Var Definition i=demandinperiodi ndtimeunit.Month123456789101112Demand30070080090033002006009002003001000800MethodNumberofOrdersMonthsthatanOrdersarePlacedTotalHoldingCostsTotalOrderingCost TotalCost1. EOQ2.MILPbsedonEndingInventory3.MILPbsedonAverageI Mealheuristic7.Wagner-WhitinAlgorithm
1 Objectives 1. Investigate a more complex arithmetic circuit; 2. Understand, design, and verify a SystemVerilog array multiplier to perform unsigned multiplication using partial products; 3. Build an arithmetic logic unit (ALU) that can perform four different operations; and 4. Design a sequential SV controller to manage shared resources (“bus”) using staged operations with intermediate registers. 2 Pre-Laboratory Procedure 2.1 Read the entire lab procedure and Chapter 5.2 in your book (ALU, Multiplication) in your book; 2.2 The following will be turned in, as a group, to a D2L dropbox in your lab section before 2 p.m. on your lab day the week of Oct. 31. Complete these items (in this lab manual) for your pre-lab: • 3.1, 3.2, 3.3, 3.4 • 4.3, 4.4 2.3 Bring soft copies of all your SV modules to lab to be compiled and loaded onto the FPGA for testing and demonstration. For your SV, you must use separate modules with one .txt file per Verilog module for the various logic functions and memory elements. Do not .zip your pre-lab files, and do not turn in your SV in ‘.sv’ file format. You must turn these in as a ‘.txt’ file to receive pre-lab credit, ‘.sv’ files are not readable in D2L. By now you should have downloaded and installed Quartus Prime Lite. You should come to lab with Verilog modules that compile the very first time. You will ensure that your files compile correctly by compiling them at home with Quartus. A proactive student would also test that the compiled SV works on their DE10-Lite board.Figure 1: (a) Schematic of a 4-bit multiplier that implements A × B = P. (b) A representation of the partial-product and sum method of unsigned binary multiplication. (c) A 4-bit array multiplier for unsigned binary numbers using partial products (AND gates) and cascaded full-adders. 3 4-Bit Unsigned Array Multiplier Procedure The goal of this section is to design a 4-bit unsigned integer multiplication circuit in SystemVerilog. The multiplier circuit will take two 4-bit inputs (the multiplicand, A, and multiplier, B) and return an 8-bit output (the product, P). The inputs, A and B, will each be implemented using four switches. The 8-bit product, P, will be displayed on two 7-segment displays in hexadecimal. 3.1 As part of pre-lab, complete the “pre-lab” column of Table 1.Figure 2: A 4-bit partial-product calculator for row i of the array multiplier. The partial product is calculated using the multiplicand A, bit i of the multiplier Bi, and the partial product output of the previous row PP4:1,i−1. The output is the next partial product PP4:1,i, and the product bit Pi. 3.3 Create a second SV file named “mult4.sv” that contains one SV module named mult4. Using structural SV, connect four PP4 modules together to make a 4-bit array multiplier as shown in Fig. 3Figure 3: A 4-bit array multiplier that calculates A × B = P, where A and B are 4-bits wide and P is 8-bits. 3.4 Make a top-level SV file that connects the mult4 module. Assign SW[7:4] as your A input and SW[3:0] as your B input. Connect A, B, and P to 7-segment displays using a hex decoder (note: you should already have one of these from a prior laboratory experiment. If not, you need to create a 4-input combinational circuit that outputs 0-F on an active-low 7-segment display for the inputs 00002 − 11112). You will need one hex digit for each of your A and B inputs, and two digits for your P output. 3.5 Load your top-level SV module to your FPGA. Verify the operation of your SV module by checking that the outputs match your pre-lab in Table 1. If they do not, either debug your SV, recalculate your pre-lab, or both. Table 1: Unsigned multiplication A B Pre-lab Product A×B FPGA Product A×B decimal binary hex decimal binary hex decimal binary hex decimal binary hex 1 0001 1 10 1010 A 10 1010 A 10 1010 A 3 0011 3 15 1111 F 45 00101101 2D 45 00101101 2D 6 0110 6 11 1011 B 66 01000010 42 66 01000010 42 13 1101 D 5 0101 5 65 01000001 41 65 01000001 41 9 1001 9 2 0010 2 18 00010010 12 18 00010010 12 15 1111 F 15 1111 F 225 11100001 E1 225 11100001 E1 4 Arithmetic Logic Unit (ALU) Procedure The goal of this section is to design an ALU, and add some additional hardware to share physical resources by controlling access in multiple stages using a sequential controller. Dr. Hansen will provide you the top-level SV file and module headers for the project. The ALU will use a 2-bit control signal, ALUControl, to select from one of four operations, given in Table 2. Table 2: ALU Operations ALUControl Operation 2’b00 ADD 2’b01 SUB 2’b10 AND 2’b11 OR 4.1 Download the provided SV files from the D2L Laboratory 7 page. 4.2 The top-level SV file and module (“ALUcontroller.sv”) has been completed for you by Dr. Hansen (except the 7-segment connections), implementing the hardware shown in Fig. 4. Not pictured are the clock debouncer (CLKb to CLKb deb), controller (to determine active-high register enables), and the 7-segment hex decoders. You will need to replace the placeholder 7segment structural SV in the ALUcontroller module with your 7-segment module definition.Figure 4: The top-level schematic for the ALU controller. The INPUT bus is shared between the A and B inputs to the ALU, with the A and ALUcontrol inputs buffered by a register. A controller module (not pictured) is used to determine the active-high register enables enA, enC, and enALU (green) to control the operation of the negative-edge triggered registers (triggered by a debounced clock signal, CLKb deb). 4.4 Complete the controller module in “controller.sv” using any SV you wish. This sequential controller takes as an input the debounced clock signal to count the operation step. Based on the current step, a combinational logic circuit determines the enA, enC, and enALU control signals. The required steps are: a. save the INPUT to register A and save the ALUcontrol bits b. save the result of A op B to the C register, and V,C,Neg,Z to the ALU status register (where A and op were the values saved from step a.), and B is the current value of the INPUT 4.5 Assign the top-level I/O to the DE10-Lite board as described in Table 3. Note that the 7-segment outputs (Aseg, Bseg, and Cseg) are 2 × 7 two-dimensional signals. The first index chooses the HEX digit (0 or 1), and the second index chooses the segment (0 – 6, relating to the 7 segment display a–g). Table 3: Required DE10-Lite Input/Output Signal DE10-Lite I/O INPUT SW[7:0] ALUcontrol SW[9:8] CLKb KEY0 CLK50M 50 MHz clock Aseg[1][0:6] HEX5 Aseg[0][0:6] HEX4 Bseg[1][0:6] HEX3 Bseg[0][0:6] HEX2 Cseg[1][0:6] HEX1 Cseg[0][0:6] HEX0 V,C,Neg,Z LEDR[3:0] Laboratory 7 Signoff Sheet 3.6 4.7
1 Objectives 1. implement hierarchical modules for Latches and Flip-Flops in System Verilog; 2. Clean noisy inputs using a debouncer module; 3. Practice SV, Quartus, and FPGA design, implementation, and testing.2 Pre-Laboratory Procedure 2.2 Complete these items (in this lab manual) for your pre-lab: • 3.1.1.1, 3.1.1.2 • 3.1.2.1, 3.1.2.2 • 3.2.1.1 • 3.2.2.1 • 3.2.3.1 2.3 Bring your circuit diagrams, block diagrams and bring soft copies of all your SV modules to lab to be compiled and loaded onto the FPGA for testing and demonstration. You can come to lab with SystemVerilog modules that compile the very first time. You will ensure that your files compile correctly by compiling them at home with Quartus. A proactive student would also test that the compiled SV works on their DE10-Lite board (allowing the student to leave early!).3 Laboratory Procedure We will investigate the sequential circuits discussed in class using the Intel DE10-Lite FPGA boards. Recall that latches are level-sensitive memory elements, and flip-flops are edge-triggered.3.1 Latches 3.1.1 SR-LatchFigure 1: A 1-bit SR-Latch using cross-coupled NOR gates. The characteristic table shows the four possible cases.3.1.1.1 Read Section 3.2.1 of your textbook. 3.1.1.2 Create a SV file named “sr_latch.sv” that contains one SV module named sr_latch. Write behavioral SV to describe the operation of a SR-latch.3.1.1.3 Compile the SR-Latch SV using Quartus Prime Light. Assign switches SW[1:0] to the S and R inputs, and LEDR[1:0] to monitor the outputs Q and ̄Q.3.1.1.4 Load the SR-Latch to your FPGA. Verify the operation of your SV module by checking every possible input combination. Record these values in a truth table and compare to the expected values.3.1.2 Gated D-Latch 3.1.2.1 Read Section 3.2.2 of your textbook.Figure 2: (a) A 1-bit Gated D-Latch using a clock signal and an SR-Latch. (b) The characteristic table shows the possible cases.3.1.2.2 Create a SV file named “d_latch.sv” that contains one SV module named d_latch. Write behavioral/structural SV to describe the operation of a D-latch using your SR-Latch module. 3.1.2.3 Compile the D-Latch SV using Quartus Prime Light. Assign switches SW[1:0] to the D and CLK inputs, and LEDR[1:0] to monitor the outputs Q and ̄Q’. 3.2 Flip-Flops For all SV portions of this section, you will need to debounce the noisy clock signal that will come from your KEY[0] button. Because the key is mechanical, when pressed the electrical contact bounces multiple times before settling to the correct value. You can see an o-scope capture of the noisy key inputs from your DE10-Lite Board in Fig. 3. If this signal is directly input to a circuit that relies on a clock (CLK), that circuit will see multiple active CLK edges and malfunction. To overcome this, a debouncer circuit or SV module can be used so that only one clean CLK edge is seen by your circuit. Mr. Galipeau has provided a SV module called debouncer for you to accomplish this for this lab and Project 1 (“debouncer.sv”). The module takes two inputs (A_noisy and CLK50M) and outputs the clean signal A. The DE10-Lite inputs for the module are provided in Table 3.2. The output should be connected to your internal CLK logic.Table 1: Inputs for the debouncer module. Module Input DE10-Lite Input Pin A-noisy KEH[0] PIN_B8 CLK50M 50 MHz Clock PIN_P11Figure 3: The noisy key input of the DE10-Lite board captured on the oscilloscope.Figure 4: A 1-bit positive-edge triggered D Flip-Flop using a master-slave configuration of two gated D-latches. 3.2.1 D Flip-Flop 3.2.1.1 Read Section 3.2.3 of your textbook. 3.2.1.2 Create a SV file named “d_ff.sv” that contains one SV module named d_ff. Write behav- ioral/structural SV to describe the operation of a D-FF using two of your gated D-Latch modules. 3.2.1.3 Create a top-level file called “ff_toplevel.sv” that connects SW[0] to the D input of your D-FF and LEDR[1:0] to monitor the outputs Q and ̄Q. Connect the debouncer module between KEY[0] and the CLK input of your D-FF.3.2.2 T Flip-Flop A T Flip-Flop, or toggle Flip-Flop, holds the prior value on the active clock edge if T = 0, otherwise it toggles its output if T = 1. This component is useful in counting circuits, clock circuits, and more. There is no discussion in your book, but you can read about them here: https://www.electronicshub.org/t-flip-flop/.Figure 5: A 1-bit positive-edge triggered T Flip-Flop. 3.2.2.1 Create a SV file named “t_ff.sv” that contains one SV module named t_ff. Write behav- ioral/structural SV to describe the operation of a T-FF using your D Flip-Flop module.3.2.2.2 Replace the D-FF in “ff_toplevel.sv” with your T-FF module. 3.2.3 JK Flip-Flop A JK Flip-Flop is known as a universal flip-flop because you can use them to create a D or T flip-flop. When building finite state machines, JK flip-flops can be used to greatly simplify your state transition logic. As most digital design is now performed on programmable logic devices, JK flip-flops have fallen out of favor for the simpler D flip-flop.Figure 6: A 1-bit positive-edge triggered JK Flip-Flop.3.2.3.1 Create a SV file named “jk_ff.sv” that contains one SV module named jk_ff. Write be- havioral/structural SV to describe the operation of a JK-Flip-Flop using your D Flip-Flop module. 3.2.3.2 Replace the T-FF in “ff_toplevel.sv” with your JK-FF module. Assign switches SW[1:0] to the J and K inputs.Lab Check off Pre Lab Points SR Latch 5 D Latch 5 D Flipflop 5 T Flipflop 5 JK Flipflop 5 Lab Demos SR Latch 10 D Latch 10 D Flipflop 10 T Flipflop 10 JK Flipflop 10 total 75
1 Objectives We will: 1. simplify logic circuits using Boolean theorems; 2. investigate the relationship between minterms, Maxterms, sum-of-products (SOP) implementation, and product-of-sums (POS) implementation; 3. prove that SOP and POS circuits can be built using only NAND and NOR gates, respectively. 2 Pre Lab To be completed before your lab meets (individually): 2.1 Read the entire lab procedure. • 3.1.1, 3.1.2, 3.1.3 • 3.2.1, 3.2.2 (pre-lab column), 3.2.3, 3.2.4, 3.2.5, 3.2.6 • 3.3.1, 3.3.2, 3.3.3 2.3 When you reduce an expression, show your work (write the number of each theorem/axiom used, one per line). 3 Lab Procedure 3.1 Simplification using DeMorgan’s Theorems 3.1.1 Complete the “F(A,B,C) original by-hand” column of the truth table in Table 1 for the following function (remember the order of operations! parentheses → NOT → AND → OR): F(A,B,C) = (A′ + B′ · C)′ · (A′ + B′ · C′)′ (1) 3.1.2 Draw a logic diagram for the function in Eq. 1 using AND, OR, and NOT gates (remember the order of operations!). 3.1.3 Create a SV file named “functionABC.sv” that contains one SV module named functionABC. Write structural SV using the built-in logic gate modules to describe the operation of the circuit you created. Label any logic wires required. 3.1.4 Compile the SV using Quartus Prime Lite. Assign switches SW[2:0] to the three inputs (SW[2] as MSB A, SW[0] as LSB C), and LEDR0 to monitor the output. 3.1.5 Load the circuit to your FPGA. Verify the operation of your SV module by checking every possible input combination and filling in the “F(A,B,C) original on DE10” column of Table 1. Check that the output matches the column you calculated by hand. If they do not match, double check both the SV and the original truth table and correct the output. Table 1: Truth Table for F(A,B,C) A B C F(A,B,C) original F(A,B,C) original F(A,B,C) canonical by-hand on DE10 (or reduced) on DE10 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3.1.7 Based on your results (in Table 1), write an equivalent expression for the circuit as the canonical sum-of-products: 3.1.9 Compile the SV using Quartus Prime Lite. Assign switches SW[2:0] to the three inputs (SW[2] as MSB A, SW[0] as LSB C), and LEDR0 to monitor the output. 3.1.10 Load the circuit to your FPGA. Verify the operation of your SV module by checking every possible input combination and filling in the “F(A,B,C) canonical (or reduced) on DE10” column of Table 1. Check that the output matches the other two columns. If they do not match debug your canonical sum-of-products expression or SV. 3.2 Boolean Simplification 3.2.1 Examine the circuit in Fig. 1 and write the Boolean expression for the output, F.Figure 1: Circuit to Simplify: F(w,x,y,z) 3.2.2 Complete the “Original F theory-Pre Lab” column of the truth table for F in Table 2. 3.2.3 Create a SV file named “functionWXYZ.sv” that contains one SV module named functionWXYZ. Write structural SV using the built-in logic gate modules to describe the operation of the circuit you created. Label any logic wires required. 3.2.4 Simplify the expression you obtained above, using Boolean theorems. Your lab report should show each step of this simplification, and you should list the theorem (or axiom) used in each step. Draw a logic diagram for the simplified expression. 3.2.5 Create a SV file named “functionWXYZsimplified.sv” that contains one SV module named functionWXYZsimplified. Write structural SV using the built-in logic gate modules to describe the operation of the circuit you created. Label any logic wires required on your diagram. 3.2.7 Create a third SV file named “fWXYZtoplevel.sv” that contains one SV module named fWXYZtoplevel. Add all three SV files to the same Quartus project, where the project should also be named fWXYZtoplevel. Use structural SV and explicit port mapping to connect together functionWXYZ and functionWXYZsimplified to the inputs and outputs of your DE10-Lite board. Table 2: Truth Table for various implementation of F(w,x,y,z) w x y z Original F Original F Simplified F theory-Pre Lab empirical empirical on DE10 on DE10 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 3.2.8 Compile the SV using Quartus Prime Lite. Assign switches SW[3:0] to the four inputs (SW[3] as MSB W, SW[0] as LSB Z) in the fWXYZtoplevel as inputs to both functionWXYZ and functionWXYZsimplified modules. Connect LEDR1 to monitor the output of functionWXYZ and LEDR0 as the output of functionWXYZsimplified. 3.2.9 Verify the operation of your modules by checking every possible input combination. Record these values in the appropriate columns of Table 2. If the two outputs do not match, debug your Boolean algebra and/or SV modules. 3.3 SOP and POS Implementations Consider the following function: f(A,B,C) = Xm(0,1,5) 3.3.1 Write this function as a canonical sum-of-products and design the corresponding circuit. Fill out the “F(A,B,C) original by-hand” column of Table 3. 3.3.2 Express the function as a list of Maxterms (or shorthand using our Q notation), give the corresponding canonical product-of-sums, and design the corresponding circuit. 3.3.3 Use Boolean algebra to simplify both of the above expressions to determine the minimal sumof-products and the minimal product-of-sums representation for the above function. Draw the corresponding logic diagrams for the minimal SOP and POS, including first-level inverters. Table 3: Truth Table for F(A,B,C) A B C F(A,B,C) original F(A,B,C) NAND F(A,B,C) NOR by-hand SOP circuit POS circuit 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Laboratory 2 Signoff Sheet Student Name (Print in Black Ink): To be turned in (scan a copy) with your lab report (back sheet) to D2L. 2.4 3.1.6 3.1.12 3.2.10 3.3.3 Lab Completed: by signing this, I affirm on my honor that I am aware of the student disciplinary code and that I have successfully completed this laboratory assignment.
Lab 1 Digital Logic & DeMorgan’s LawI. ObjectivesA. Investigate rise time and fall time of waveforms measured on an oscilloscope. B. Learn how to specify, synthesize, download and test circuits on a DE10-Lite FPGA board using Verilog. C. Build circuits to verify DeMorgan’s theorems.II. Pre-Lab It is important to complete the pre-lab work before lab so that you can finish the lab on time. Read this entire lab, and with the following guidelines, determine which portions can be done prior to lab.Generally, prior to lab you should: 1. Perform any algebraic simplification and circuit design that is required. 2. If a circuit is to be made during lab, arrive with the circuit diagram showing what to build. 3. If any theoretical values are required, calculate and tabulate them prior to lab.For this lab: 1. Install Quartus as part of your pre-lab work. During this lab, you’ll use Quartus to create circuits that verify DeMorgan’s Theorems, using your DE10-Lite boards. You’ll need to install the Quartus software that we use to create circuits for the boards. Detailed directions are posted in both the Class and Lab D2L shells. Please follow the directions exactly.A. Rise/Fall TimesDuring the first part of this lab, you will investigate the rise/fall times of waveforms as they move through digital components.Take a few minutes to read about rise and fall time for digital circuits on the web this is a good source. https://en.wikipedia.org/wiki/Rise_time. As pre-lab work, answer the following questions.1. Explain rise time. ___5 pts2. Explain fall time. ____ 5 ptsB. View the video at the link below, which shows how to measure rise time and fall time with an oscilloscope and use it to answer the questions below: https://www.youtube.com/watch?v=knvscPTVdv41. What is the rise time of the waveform in the video and how was it calculated? ___5 pts2. What is the fall time? ___ 5pts3. Why do we measure from 10% to 90% instead of from 0% to 100%? ___ 5 ptsIII. LabC. Most of the labs in this course require you to write Verilog statements to specify circuits, synthesize them, download them into the DE10-Lite board and test them.In this lab, we’ll create circuits to verify DeMorgan’s Theorems. Circuit diagrams for Part 1 of DeMorgan’s Theorem are shown below.Figure 1: Part 1 of DeMorgan’s Theorem1. Construct the circuits shown in Figure 1. Use the pin planner to connect each input to a switch and the outputs to an LEDs. Label your connections in the blanks below ___ 10 ptsA = _____ B = _____ Y =_______ Z=_____2. Use the switches to obtain each combination in Table 1 below and record the output you observe.A B Y Z 0 0 0 1 1 0 1 1Table 1: Truth Table for NOR4. Now, construct the circuit on the right-hand side of Figure 2(a). Connect each input to a switch and connect the output to an LED. Use the switches to obtain each combination in Table 2 below, and record the output you observe.A B Y Z 0 0 0 1 1 0 1 1 Figure 2: Part 2 of DeMorgan’s TheoremTable 2: Truth Table for NANDIV. GradeActivity points total Pre Lab A 10 Pre Lab B 15 NOR 20 NAND 10 Total 55
BACKGROUND:Welcome to the GA Tech bookstore website. It’s a place where you can read and review all of the classics. The creators of the website were pretty junior but ambitious. They created the website in only 2 days! They knew a few things about security and did their best but left some vulnerabilities behind. Your job is to seek these out and find the problems.SETUP:To get set up for the flags, carefully follow the steps below. Log into the VM with the websec user.The password should be in Canvas.Run this at the terminal to start the Bookstore Website./StartContainer.shTESTING:You will need to execute a StudentGrader script to test your exploits for all flags. The StudentGrader is a script that willRun this at the terminal to test your exploit for a flag./StudentGrader.sh –flag X –gaTechId Y –filePath ZHere are the valid parameters for the StudentGrader scriptYou will be learning about modern web based security vulnerabilities in this project. A majority of the attacks are based on the OWASP Top 10 list which is produced and updated every few years.In particular we will cover these learning topics:The final deliverables:A single JSON formatted file will be submitted to Gradescope.See Submission Details for more information.Important Reference Material:Virtual Machine:TABLE OF CONTENTSYou’ve stumbled upon a publicly available web page that is not finished. It seems like the developers are still working on it but somehow published it to production by accident. The page does not have a link in the main menu so the developers thought no one would find it. Challenge accepted!Download the required starter template from the VM using Chrome here:To earn your flag you must alter the template so that it performs these steps when you open it in a browser or run it using the grader:HINTS:FLAG TESTING:To test your flag1.html file and receive the flag, run this command at the command line. Note: replace the gaTechId with your actual GTID../StudentGrader.sh –flag 1 –gaTechId 923456789 –filePath /home/websec/Desktop/flag1.html Your web output will look similar to this: Congratulations, you’ve made it this far! Now you’ve noticed some strange behavior. You were experimenting with reviews and found you can post basic html tags and images in the reviews! The developers of the site wanted reviews to be a rich user experience and not just plain text. With great power comes great responsibility though. You’ve found a way to nefariously inject code that runs when any victim loads a page with your exploited review.This flag will introduce you to the basics of XSS (Cross-Site Scripting) attacks. Specifically you’ll leverage these:Download from the WebSec VM the required starter template here:To earn your flag you must alter the template so that it performs these steps when you open it in a browser or run it using the grader.HINTS:FLAG TESTING:To test your flag2.html file and receive the flag, run this command at the command line. Note: replace the gaTechId with your actual GTID../StudentGrader.sh –flag 2 –gaTechId 923456789 –filePath /home/websec/Desktop/flag2.htmlNote: The grading script will reset the database before it executes your file. Be prepared as any data you have created will be lost.Your web output will look similar to this:Malicious user input can be provided using the same techniques, but through different attack vectors. You’ve already persisted malicious data in a review and want to see if there are any other areas of the site that are susceptible to data manipulation. Using your newly acquired XSS skills, you go hunting for more ways to perform this method of attack.In order to successfully exploit another XSS attack, you will need to figure out another way the site accepts user input and employ a similar technique to perform what’s called a reflected XSS attack. This means the XSS code does not reside in the webpage and does not persist, but is malicious code input in the request and returned in the response. You notice there is a page that allows the user to search for a book and wonder if this page can be exploited.Your goal is to display a javascript alert containing the text CS6035 on the search page.You can use the same XSS resources from the previous flag in addition to reflected XSS resources:Download from the WebSec VM the required starter template here:To earn this flag by performing the following steps:HINTS:https://github.gatech.edu/pages/cs6035-tools/cs6035-tools.github.io/Projects/Web_Security/Flag3.html 1/2 2/17/25, 2:35 AM Flag 3 | CS 6035FLAG TESTING:To test your flag3.html file and receive the flag, run this command at the command line. Note: replace the gaTechId with your actual GTID../StudentGrader.sh –flag 3 –gaTechId 923456789 –filePath /home/websec/Desktop/flag3.html Your web output will look similar to this:Congratulations on reaching this stage! You’ve already navigated through various challenges, and now it’s time to delve into the intricacies of Cross-Site Request Forgery (CSRF) attacks. CSRF is a type of attack that tricks a user into submitting a request to a web application where they are authenticated without their knowledge or intent. This can lead to unauthorized actions being performed on behalf of the user.For further exploration and a deeper understanding of CSRF and its prevention, consider the following resources:You’ve learned of a vulnerability that exists on the bookstore website. It appears you can craft an html file that resets a user’s password to one of your choosing when they open it. You plan to embed this file in an email and see who actually clicks on it. They’ll never know!Download from the WebSec VM the required starter template here:You must reset an unsuspecting user’s password to HanSolo77 Note: You will not know who the user is so your crafted html file should work for any user of the website.Earn this flag by performing the following steps:Hints: FLAG TESTING:To test your flag4.html file and receive the flag, run this command at the command line. Note: replace the gaTechId with your actual GTID../StudentGrader.sh –flag 4 –gaTechId 923456789 –filePath /home/websec/Desktop/flag4.html Your web output will look similar to this:The developers built an Admin page for power users of the site. Obviously, they couldn’t just let everyone have access to this page so they built a simple RBAC (Role-based access control) system and put it into place. Unfortunately for them, they didn’t do the best job of building these permissions and it can be bypassed! Your job is to bypass any security checks and gain access to this Admin page.The Admin page can be accessed by clicking the link at the top right of the page. In order for this to work correctly in your html file, you may need to write a little JavaScript and find a place where this can be XSS injected. Knowing these developers, I bet they left some clues. Maybe some files they should have removed before production.Download from the WebSec VM the required starter template here:To earn your flag you must alter the template so that it performs these steps when you open it in a browser or run it using the grader:1 Bypass all permissions checks and open the Admin page fully loaded a Note: You must do all of this in the html template and it must automatically load/open the pageb The URL must start with http://localhost:7149/adminHints:https://github.gatech.edu/pages/cs6035-tools/cs6035-tools.github.io/Projects/Web_Security/Flag5.html 1/2 2/17/25, 2:36 AM Flag 5 | CS 6035FLAG TESTING:To test your flag5.html file and receive the flag, run this command at the command line. Note: replace the gaTechId with your actual GTID../StudentGrader.sh –flag 5 –gaTechId 923456789 –filePath /home/websec/Desktop/flag5.html Your web output will look similar to this:Congratulations on making it this far! You’ve already overcome several obstacles, and now it’s time to dive into Cross-Origin Resource Sharing (CORS). CORS is a security feature in web browsers that allows applications to request resources from domains other than the one hosting the application.To complete this task, we’ll be working with a different flavour to CORS. Specifically, we will explore how CORS can limit the type of requests that can be made and how expanding on the allowed access control methods will help accomplish this task.Download the required starter template here:Your goal is to update the title of book 6 to “Let the fun begin!” and redirect to its Detail View. This needs to be done using JavaScript only. Use this endpoint to make the update:PUT api/book/{bookId}Body:{“newTitle”: “Title 2” }Did the attempt fail? Investigate and troubleshoot—think about what might have gone wrong.Ensure your script addresses the issue and updates the book title. Once you’ve successfully updated the book title, submit the script and earn your flag!Hint:Identify an endpoint that can assist you in configuring the CORS allowed methods.FLAG TESTING:https://github.gatech.edu/pages/cs6035-tools/cs6035-tools.github.io/Projects/Web_Security/Flag6.html 1/2 2/17/25, 2:36 AM Flag 6 | CS 6035To test your flag6.html file and receive the flag, run this command at the command line. Note: replace the gaTechId with your actual GTID../StudentGrader.sh –flag 6 –gaTechId 923456789 –filePath /home/websec/Desktop/flag6.html Your web output will look similar to this:The grader from the output will look similar to this. Copy the flag to flag6 in project_websecurity.json.Disclaimer: You are responsible for the information on this website. The content is subject to change at any time. © 2024 Georgia Institute of Technology. All rights reserved.https://github.gatech.edu/pages/cs6035-tools/cs6035-tools.github.io/Projects/Web_Security/Flag6.html 2/2
This project aims to enhance password security by incorporating a second authentication factor (2FA). We’ll explore this concept by modifying the Linux login implementation. While the specific implementation may be simplified for educational purposes, the underlying principles are similar to password hardening techniques discussed in class. Here’s what you’ll learn:Focus:This project concentrates on improving login security for local desktops/laptops. However, the concepts can be extended to secure remote logins as well. We’ll be using a pre-configured Ubuntu virtual machine (VM) compatible with Oracle VM VirtualBox 7.0. You can directly import this VM into VirtualBox for your work.The VM has a pre-created user account named “cs6238” with standard user privileges. To access files requiring root access, open a terminal and type:Enter the password for “cs6238” (note: the password itself is not shown here for security reasons). Once you have root access, locate the desired file.Default Credentials:Project Files:The cloned repository contains: Figure 1. Desktop folder Content Important Note:Understanding Linux Login System (Pre-requisite):Before proceeding, familiarize yourself with the following aspects of the Linux login system:There are plenty of online resources for these topics. The “GETTING STARTED ON LINUX LOGIN/PASSWORDS” section in the Appendix can serve as a starting point.We’ve provided two Python code files to help you understand how the system works for creating and logging in users:Once you understand these scripts, you’re ready for the main project task. This task focuses on implementing a 2FA system using a provided token_generator (TG) executable. While typical 2FA systems use a unique device per user (like a phone), this project uses a single TG for all user accounts. Each user will have two accounts: one in the 2FA system and one with the TG (registered with a PIN).You are provided with the compiled token_generator executable. You do not need to implement it; you only need to understand its interface and use it as a black box.The TG offers three options:Important TG Behavior:After each TG operation, the TG will prompt for confirmation. If the corresponding 2FA operation is successful, enter ‘y’ or ‘Y’. Otherwise, entering any other character will cause the TG to revert to its previous state.The 2FA method involves four main operations: creating a user, logging in, updating, and deleting a user./etc/shadow.Important: Adhere to the specified prompt order. Regrade requests based on incorrect prompt order will not be accepted.You must create a standalone Python program (2FA.py) based on the provided Python code. Your program must implement the following:o Prompt the user to select an action:▪ Select an action:(IT)./etc/shadow and /etc/passwd files and creating a home directory. o On success, print “SUCCESS: created”. o The salt remains the same unless the user updates the password or deletes and recreates the account.o Request Username, Password, New Password, Confirm New Password, New Salt, Current Token (CT), and Next Token (NT).o Request username, password, and current token.Important Considerations:Perform a security analysis of the implemented 2FA method, addressing the following points: This file should contain your Python code implementing the 2FA functionality based on the provided description. It should handle user prompts, and perform the necessary security checks during user creation, login, update, and deletion operations.This PDF report, named according to your GT ID (e.g., jrodriguez_2FA.pdf), should detail the security analysis of the implemented 2FA system. It should address:o Server-Client Implementation and Secure Token Transfer:By covering these points in your report, you’ll demonstrate a comprehensive understanding of the 2FA system’s security implications and potential improvements.Important Notes: o If you’re unfamiliar with importing VMs, refer to the provided Oracle VM VirtualBox documentation:https://docs.oracle.com/cd/E26217_01/E26796/html/qsimport–vm.html Figure 1: Creating an Account Figure 2: Logging into an Account Linux User Creation and Password Storage:When creating a new user, the Linux system prompts for a password. Depending on the Linux distribution and its configuration, one of several hashing algorithms is used for password encryption. The system generates a random salt, which is then used to create a one-way hash of the password. This hash, along with other user details, is stored in the /etc/shadow file.Example User Entry in /etc/shadow:cs6238:$6$Cl7HxrVPp7LvCHDb$km3WARvkSdd7toH5lS/OoU5mlSk4.F9ImoQ8H 5Cy5ii10klGO5TCTy9tOZCZFRko6EGM1uIEtwn2f6MN8MLA8/:19589:0:99999:7:::Structure of a User Entry:Each user entry in /etc/shadow consists of nine fields separated by colons (:).User Account Information in /etc/passwd:After storing the password hash in /etc/shadow, the system creates a home directory for the new user and adds an entry to the /etc/passwd file. This file stores essential user account information needed during login. Each line in /etc/passwd represents a user account.Example User Entry in /etc/passwd:cs6238:x:1000:1000:cs6238:/home/cs6238:/bin/bashStructure of a User Entry:Each entry in /etc/passwd consists of seven fields separated by colons (:):Project Relevance:For this project, it is sufficient to understand the basic structure and purpose of the /etc/passwd file, especially the username and home directory fields. Further exploration of the details of the /etc/passwd file is encouraged but not strictly required for completing the project.User Creation Completion:After updating the entry in the /etc/passwd file and creating the user’s home directory, the user creation process is complete. Table of ContentsProject II: Strengthening Login Security with Two-Factor Authentication (2FA)……………………………………. 1 Learning Objectives:…………………………………………………………………………………………………………… 1 Project Setup:…………………………………………………………………………………………………………………… 2 Task 1: Implementing 2FA (80% of grade)………………………………………………………………………………… 4 Token Generator (TG):……………………………………………………………………………………………………… 4 The 2FA Method:……………………………………………………………………………………………………………. 4 Implementation of the 2FA method:…………………………………………………………………………………… 5 Task 2: Security Analysis of 2FA (20% of grade)…………………………………………………………………………. 8 Project deliverables for your 2FA implementation:…………………………………………………………………….. 9 Appendix…………………………………………………………………………………………………………………………… 10
Who You are allowed to do this assignment with a partner if you want. There is a maximum of 2 people per team. Background Create an application suite (a system) that consists of three distinct processing components: • a “data creator” (DC) application – call the application DC • a “data reader” (DR) application – call the application DR • a “data corruptor” (DX) application – call the application DX In this system’s development, you will design and implement the data creator application, the data reader application, and the data corruptor application. The purpose of this assignment is to force all involved in the solution to see how / why and when certain IPC mechanisms are used within UNIX / Linux System Application programming. That is, what IPC mechanism is better suited for performing a certain type of communication job over another form of IPC. The Team Since this is an Assignment of considerable size, I do not expect any one individual to complete this assignment on their own – in fact, I suggest that you work together with a partner : • one person can develop both the DC (client application) and the DX (corruptor application) • one person developing the DR (server application) Before you begin on the assignment, please use the A-03 Group sign-up (under the Groups option in Course Tools) to organize yourselves into partnerships. Remember that both members need to sign-up and enroll in the same group. Find a group quickly and start organizing, designing and coding your system! Please note that it is expected that both members will share equally in the mark given to your partnership’s effort. Overall Considerations This set of applications will require considerable coordinated effort between the partners. Here are a couple of other things to consider : • all applications should have modular design • all applications should have file-header and function comment blocks • as always – don’t forget the in-line comments within your code • all code developed in this project must be written in C • please hand in your code in the required directory structure with makefiles for each of the DC, DR and DX components o Please see the Linux-Development-Project-Code-Structure document in the Assignment area of eConestoga for information on how to structure the code for a more complex project consisting of multiple binaries Assign-03: Multi-Process Development The Hoochamacallit SystemData Creator Purpose The data creator (DC) program’s job is to artificially generate a status condition representing the state of the Hoochamacallit machine on your shop’s floor. Details • This application will send a message (via a message queue) to the Data Reader application (the server component of the solution). o Make sure that your DC program follow best practices and checks for the existence of the message queue before sending its first message o If the message queue doesn’t exist, then the DC application will enter a loop in which it will sleep for 10 seconds and try again to see if the message queue has been established and created o Only after the message queue has been created can the DC application enter its main processing loop o Once the existence of the queue has been established, the first message that must be sent is an Everything is OKAY type message • Each message must contain the machine’s ID value (use the PID of the process) • As well as a randomly selected status (you’ll need to read up on how the rand() function works) value (except for the 1st message) from the list below o 0 : means Everything is OKAY o 1 : means Hydraulic Pressure Failure o 2 : means Safety Button Failure o 3 : means No Raw Material in the Process o 4 : means Operating Temperature Out of Range o 5 : means Operator Error o 6 : means Machine is Off-line • this application will send such a message on a random time basis – between 10 and 30 seconds apart • in making the status value of the message random as well as the frequency of the message itself, this application’s output is not predictable o please note that the DC should not expect a response or reply message – all this application needs to do send message after message • once the DC application has generated and sent a Machine is Off-line message, the DC application may exit o until the Machine is Off-line message is randomly generated and sent, the DC continues to send message after message • while developing the DC application, feel free to have your debug output being printed to the screen. However, when you submit your final version of this application – there must be no output being printed to the screen. This application requires no input or output to or from the user. NOTE: It is expected that while running and testing your system solution, you could have multiple DC applications running. Each DC represents a different Hoochamacallit machine on the shop floor. There is a maximum of 10 different machines that need to be supported on the shop floor. Assign-03: Multi-Process Development The Hoochamacallit SystemData Reader Purpose The data reader (DR) program’s purpose is to monitor its incoming message queue for the varying statuses of the different Hoochamacallit machines on the shop floor. It will keep track of the number of different machines present in the system, and each new message it gets from a machine, it reports it findings to a data monitoring log file. The DR application is solely responsible for creating its incoming message queue and when it detects that all of its feeding machines have gone off-line, the DR application will free up the message queue, release its shared memory and the DR application will terminate. Details • This application is solely responsible for the creation and destruction of its message queue and shared memory o When the DR application starts: It will follow best practices and check for the existence of its message queue, and if not found, will create it Also it will create enough space in shared memory for the master list as indicated below Then it will sleep for 15 seconds, before beginning its main processing loop (this is to give you time enough to launch some DC clients and have them begin to feed the DR with messages) • The DR will create and maintain a master list of all clients that it has communication contact with o This list will be implemented as a structure. This structure needs to hold the following data elements The first element needs to contain the message queue ID value that the DR and DC processes are using to communicate The second element will represent the number of DC processes currently communicating with the DR See the Proposed DR Master List definition at the end of this document o This master list must be implemented in shared memory It will be the responsibility of the DR process to create / allocate enough space for this shared memory based upon the key_value gotten with the call • shmKey = ftok(“.”, 16535); o Things to watch out for in this master-list When the DR recognizes that it hasn’t heard from a DC application for more than 35 seconds, it removes it from the list as assumes that something bad has happened to that DC • You will need to manipulate the value in element 2 of this list (the number of DC processes currently in communication) • You will need to remove the DC identifier (and any other information about the DC) from the list of DC clients. When you remove a DC from this list – you will collapse the information of all subsequent DCs to make sure that each remaining DC identifier is in an adjacent element of the list o ie. No blank elements – see example below • The DR needs to log the removal of a DC in the data monitoring log as a “DC-YY [XXX] removed from master list – NON-RESPONSIVE” (where YY is the 1-indexed ID of the DC in the master list and XXX is the PID of the DC being removed) [NOTE: In all logging messages given below, “YY” represents the 1-indexed ID of the DC and “XXX” represents the PID of the DC] • With each message that comes in from a DC application, the DR application will perform the following 4 operations inside its main processing loop … Assign-03: Multi-Process Development The Hoochamacallit System1. Check its master list of machines to see if this new message is from a machine ID that has not been seen before If it is new, then it adds the machine ID to its list • This event is logged as “DC-YY [XXX] added to the master list – NEW DC – Status 0 (Everything is OKAY)” If this machine is known, it updates the record for this machine in the master list to keep track of the time that this message came in – to monitor the last time the DR has heard from each machine • This event is logged as “DC-YY [XXX] updated in the master list – MSG RECEIVED – Status ZZ (aaaaaaaaa)” (where “ZZ” represents the random message sent by the DC and “aaaaaaaaa” represents the textual description of the status) • In the event that the message status is a value of 6 (meaning the DC has gone off-line), then the DR will instead log the event “DC-YY [XXX] has gone OFFLINE – removing from master-list” No reply message needs to be sent to the sending DC process 2. The DR will check in its master list to see if it has been more than 35 seconds since the last time it heard from any of the machines If so, it can assume that that machine is dead and off-line or it exploded (you know those Hoochamacallit machines ) and the DR can remove that machine from its master list • Remember to properly collapse the master-list elements so that adjacent elements in the list still contain valid DC identifiers • For example : o If your DR is talking to 5 DC processes, your master-list would look like Master-element1 = msgQueueID value Master-element2 = 5 Master-DCElements[0] = DC-01 identifier Master-DCElements[1] = DC-02 identifier Master-DCElements[2] = DC-03 identifier Master-DCElements[3] = DC-04 identifier Master-DCElements[4] = DC-05 identifier o Let’s say DC-03 appears to have gone off-line – after properly collapsing the master list it would look like this Master-element1 = msgQueueID value Master-element2= 4 Master-DCElements[0] = DC-01 identifier Master-DCElements[1] = DC-02 identifier Master-DCElements[2] = DC-03 identifier [formerly DC-04] Master-DCElements[3] = DC-04 identifier [formerly DC-05] In this case, the client (DC) didn’t say they were going offline, but the server (DR) detected it – in this case the assumption that the DC is dead must be logged with the “non-responsive” logging message noted above. Note from the example above that the DC-## is basically given from the DCElements index in the array … 3. When the DR application gets an incoming message indicating that a particular machine ID has truly gone off-line, it will remove this machine from its master list (and log an “offline” event as noted above) When the number of machines registered in the master list reaches zero • the DR logs this event (i.e. that all Hoochamacallit machines have terminated and the DR is going to terminate) as “All DCs have gone offline or terminated – DR TERMINATING” • after logging this final message, the DR will remove its queue and free up its shared memory and exit Assign-03: Multi-Process Development The Hoochamacallit System the DR can assume that once a machine has sent an offline message, it will never receive another message from that machine 4. the final step in the DR’s processing cycle is to sleep for 1.5 seconds before going back to check the message queue for another message • Here is a little more information about the formatting of the required DR logging messages – every log event captured is written to a standard ASCII log file – to be found in /tmp/dataMonitor.log o each log entry must start with a timestamp (current date and time) You may find asctime() a useful function to work with (prototyped in time.h), along with localtime() as a function to query the system for the current local time o followed by the required logging event message (to capture what has happened) o the events to be logged have been indicated in the steps above. Also feel free to log any additional information that you feel would be beneficial within the log file o an example log entry should appear as follows [2018-03-06 21:05:07] : DC-02 [5687] updated in the master list – MSG RECEIVED – Status 3 (Safety Button Failure) • As with the Data Creator – feel free to have any output being printed to the screen while you are developing and debugging this application. But when you submit the code – ensure that there is no output coming from this application. Data Corruptor Purpose The data corruptor (DX) program’s purpose is gain knowledge of the resources and processes involved in the application suite and then randomly decide between a set of allowable corruptions including : • kill a DC process (to test a DC application going offline in the application suite) • to delete the message queue being used between the set of DC applications and the DR application If you really think about, the requirements (as listed above) for the DC and DR applications generally describe the happy path through the applications. The purpose of the DX application therefore is to create the alternative (or exceptions) paths through the DC and DR applications … Details • As soon as the DX application is launched, it will try to attach to a piece of shared memory which has been created by the DR process o the key to use in order to get the shared-memory ID can be gotten from the following call • shmKey = ftok(“.”, 16535); the DX will try to get the shared-memory ID value using this key • if the shared-memory piece has not yet been created by the DR, then the DX application will sleep for 10 seconds and try again. • This re-try will continue until either o 100 retries have taken place or o The DR comes online and creates the shared-memory so that the DX gets the the proper shared-memory ID o it is important that the DX application is running in the same directory as the DR application (because of the parameters used in the ftok() function call) o this piece of shared-memory will be created and maintained by the DR application. Which means that the DX application will simply be reading the information in this area of shared memory to gain knowledge of necessary information Assign-03: Multi-Process Development The Hoochamacallit System this area of shared-memory is maintained as a master list of all clients that the DR is in communication contact with This list will be implemented as indicated in the Proposed DR Master List definition at the end of this document • The DX application’s main processing loop will be comprised of the following steps: o Sleep for a random amount of time (between 10 and 30 seconds) o When it awakes, the DX should check for the existence of the message queue (between the DC’s and the DR) If the message queue no longer exists, the DX assumes that all of the DC’s have shut down and the DR (having detected this) has exited The DX will then log this event as follows, detach itself from shared memory and exit itself [2016-01-06 21:05:07] : DX detected that msgQ is gone – assuming DR/DCs done o Select an action (from the Wheel of Destruction below) randomly (you’ll need to read up on how the rand() function works) For the purposes of logging, the Wheel of Destruction will be abbreviated to WOD 00 : do nothing 01 : kill DC-01 (if it exists) 02 : kill DC-03 (if it exists) 03 : kill DC-02 (if it exists) 04 : kill DC-01 (if it exists) 05 : kill DC-03 (if it exists) 06 : kill DC-02 (if it exists) 07 : kill DC-04 (if it exists) 08 : do nothing 09 : kill DC-05 (if it exists) 10: delete the message queue being used between DCs and DR 11 : kill DC-01 (if it exists) 12 : kill DC-06 (if it exists) 13 : kill DC-02 (if it exists) 14 : kill DC-07 (if it exists) 15 : kill DC-03 (if it exists) 16 : kill DC-08 (if it exists) 17 : delete the message queue being used between the DCs and DR 18 : kill DC-09 (if it exists) 19 : do nothing 20 : kill DC-10 (if it exists) o Execute the action using whatever system call, IPC call, etc. you need to in order to get the job done When “killing” one of the DC processes – make sure to send it a SIGHUP signal • over and above this main processing loop, the DX application is responsible to logging each action that it takes in a standard ASCII log file – to be found in /tmp/dataCorruptor.log o each log entry must start with a timestamp (current date and time) You may find asctime() a useful function to work with (prototyped in time.h), along with localtime() as a function to query the system for the current local time o followed by some textual description of what has happened For example : If action 01 was randomly selected then log a message saying something like : Assign-03: Multi-Process Development The Hoochamacallit System[2016-01-06 21:05:07] : WOD Action 11 – DC-01 [7565] TERMINATED o If the DX randomly chose option 10 (the deletion of the message queue), then the DX also logs an additional event (as follows) and then detaches itself from shared memory and exits [2016-01-06 21:05:07] : DX deleted the msgQ – the DR/DCs can’t talk anymore – exiting • Also keep in mind that since this application is really an intruder application – that when trying to kill processes, delete files or remove message queues o proper error checking and handling had better be done. So that this application doesn’t crash! o For example – what if the DX is about to send a “kill” message to a DC, but the DC exits in the meantime … how with the DX handle the failure of the “kill” command? • In the final submitted version of the DX application, there should be no output to the screen Assign-03: Multi-Process Development The Hoochamacallit SystemProposed DR Master List Structure #define MAX_DC_ROLES 10 typedef struct { pid_t dcProcessID; ??? lastTimeHeardFrom; } DCInfo; typedef struct { int msgQueueID; int numberOfDCs; DCInfo dc[MAX_DC_ROLES]; } MasterList; As you can see from the above structure, you and your team are left to determine an appropriate datatype to use for the lastTimeHeardFrom data element.
